While formal verification techniques for evaluating correctness of complex algorithms such as deep neural networks (DNNs) have advanced over the years, enabling their use in safety-critical spaces such as healthcare, a significant gap remains when deploying these algorithms on embedded, resource constrained platforms: sound deployment is at odds with computational efficiencies, and numerical differences are breaking verification guarantees. First, software (SW) schemes designed for porting algorithms onto edge devices – such as quantization schemes – are either static and sound (non-optimal power consumption), or dynamic yet unsound (non-optimal for safety-critical applications). Second, hardware (HW) such as GPUs, NPUs and TPUs are designed for throughput rather than correctness of computation of security, and are as such susceptible to bit-flip attacks that can significantly alter functionality of deployed algorithms, ``silently'' breaking verification guarantees. To address both these needs we propose a both wholly new approach to real-time, dynamic and sound quantization, as well as the hardware to support it. First we developed a sound, real-time adaptive-precision quantization approach utilizing left-to-right arithmetic to pass the most significant bits (MSB) first, and dynamically adjust precision online while performing sensitivity analysis to quantify and manage the risk of decision-boundary crossings. Next, we propose a novel HW approach utilizing systolic arrays to perform left-to-right arithmetic to generate the MSB first. Together these provide a wholly novel framework for enabling not only resource-efficient neural networks and artificial intelligence at the edge, but broadly sound and resource-efficient high-precision mathematics on HW that ensures resilience to bit flip attacks on the most critical bits, and enabling carrying over of verification guarantees on algorithms from development to deployment. This work is presented as work-in-progress, with SW implementations completed and HW in-progress