This program is tentative and subject to change.

Wed 17 Jun 2026 10:40 - 11:00 at Flatirons 3 - Specification Synthesis and Verification

Modular verification tools allow programmers to compositionally specify and prove function specifications. When using a modular verifier, proving a specification about a function f requires additional specifications for the functions called by f. With existing state of the art tools, programmers must manually write the specifications for callee functions. We present a counterexample guided algorithm to automatically infer these specifications. The algorithm is parameterized over a verifier, counterexample generator, and constraint guided synthesizer. We show that if each of these three components is sound and complete over a finite set of possible specifications, our algorithm is sound and complete as well. Additionally, we introduce size-bounded synthesis functions, which extends our completeness result to an infinite set of possible specifications. In particular, we describe a size-bounded synthesis function for linear integer arithmetic constraints. We conclude with an evaluation demonstrating our technique on a variety of benchmarks. When using a modular verifier, proving a specification about a function f requires additional specifications for the functions called by f. With existing state of the art tools, programmers must manually write the specifications for callee functions. We present a counterexample guided algorithm to automatically infer these specifications. The algorithm is parameterized over a verifier, counterexample generator, and constraint guided synthesizer. We show that if each of these three components is sound and complete over a finite set of possible specifications, our algorithm is sound and complete as well. Additionally, we introduce size-bounded synthesis functions, which extends our completeness result to an infinite set of possible specifications. In particular, we describe a size-bounded synthesis function for linear integer arithmetic constraints. We conclude with an evaluation demonstrating our technique on a variety of benchmarks.

This program is tentative and subject to change.

Wed 17 Jun

Displayed time zone: Mountain Time (US & Canada) change

10:40 - 12:20
Specification Synthesis and VerificationPLDI Research Papers at Flatirons 3
10:40
20m
Talk
[SIGPLAN] Counterexample-Guided Inference of Modular Specifications
PLDI Research Papers
William Hallahan Binghamton, Ranjit Jhala University of California at San Diego, Ruzica Piskac Yale University
11:00
20m
Talk
Choose, Don’t Label: Multiple-Choice Query Synthesis for Program Disambiguation
PLDI Research Papers
Celeste Barnaby University of Texas at Austin, Danny Ding University of Texas at Austin, Osbert Bastani University of Pennsylvania, Işıl Dillig University of Texas at Austin
DOI
11:20
20m
Talk
Presynthesis: Towards Scaling Up Program Synthesis with Finer-Grained Abstract Semantics
PLDI Research Papers
Rui Dong University of Michigan, Qingyue Wu University of Michigan, Danny Ding University of Texas at Austin, Zheng Guo University of Michigan, Ruyi Ji University of Michigan, Xinyu Wang University of Michigan
DOI
11:40
20m
Talk
Verification Modulo Tested Library Contracts
PLDI Research Papers
Abhishek Uppar IISc Bangalore, Omar Muhammad IISc Bangalore, Sumanth Prabhu S Relyance AI, Deepak D'Souza IISc Bangalore, P. Madhusudan University of Illinois Urbana-Champaign, Adithya Murali University of Wisconsin-Madison
DOI
12:00
20m
Talk
Expecto: Extracting Formal Specifications from Natural Language Description for Trustworthy Oracles
PLDI Research Papers
Dongjae Lee KAIST, Kihong Heo KAIST
DOI