Designers of custom streaming accelerators traditionally use HDLs (Hardware Description Languages), but this is time-consuming and requires advanced hardware expertise. C-based HLS (High-Level Synthesis) offers a higher level of abstraction and faster design time, but still requires some hardware expertise and performance is often left on the table. A promising direction is to use HLS with high-level functional parallel patterns such as map and reduce. Prior works have shown that high performance is achievable this way. However, designing such compiler systems is challenging because the optimizer must handle a large number of language primitives and interactions between them.

This paper introduces a minimal functional IR (Intermediate Representation) for hardware design, Sirop, which can express both pipelining and spatial parallelism with just five primitives. High-level operators from prior works are represented as syntax sugar and lowered to the core language. This simplifies hardware generation and optimization.

Sirop is compared with existing compilers on a set of image processing and linear algebra benchmarks. The Sirop designs use 61% fewer ALMs (Adaptive Logic Modules) than Aetherling, 68% fewer ALMs than Shir, and 76% fewer ALMs than the Intel HLS compiler, all for the same throughput.