As the memory wall problem worsens, Near-Data Processing (NDP) has emerged to reduce data movement by computing close to data.
Recently proposed \emph{memory-mapped NDP (M$^2$NDP)} enables general-purpose NDP with low hardware overhead by extending RISC-V ISA and maximizing data parallelism with lightweight \emph{$\mu$threads}.
However, a high-level programming model for this architecture—particularly one that naturally expresses control flow across kernels—has not yet been established.

In this work, we propose a novel programming model for M$^2$NDP, called \emph{Arachne}, which explicitly expresses the mapping between $\mu$threads and the memory regions that hold the data they process.
To avoid the overhead of host-side control flow decisions among kernels executed on the device, Arachne supports flexible and efficient device-side control flow.
Furthermore, it improves programmability for expressing device-side control flow compared to existing approaches such as CUDA graphs.
Our preliminary results show that the proposed programming model reduces control-flow overhead and improves hardware resource utilization compared to conventional programming models.